Multiple chip assembly

ABSTRACT

This disclosure provides a multiple chip assembly where multiple chips are stacked on top of one another using relatively low melting temperature solder balls. Preferably, the chips (either packages or flip chip attachment) are each mounted to a substrate which is larger in lateral surface area than the associated chip. Each substrate thus has a free area, not masked by the chip, which is utilized to mount a vertically-adjacent substrate. Within this free area, solder balls connect the substrates to provide for vertical logic bus propagation through the assembly and vertical heat dissipation. The solder balls are made to have a relatively low melting temperature, permitting interconnection between chip/substrate layers without affecting connection between chip and substrate or with an intervening carrier. At the same time, the layers are compressed together during such interconnection to bring a thermal transport layer in contact between the bottom of each substrate and the chip of an underlying layer, to facilitate lateral heat dissipation.

The present invention relates to integrated circuits and, in particular,it provides a three-dimensional multiple chip assembly.

As used herein, the term "integrated circuit" ("IC") shall mean anystructure having a silicon chip, including but not limited to instanceswhere a chip is mounted on a carrier, to thereby form a "package;" theterm "IC" also encompasses attachment of a silicon chip only directly toa board.

BACKGROUND

Advances in semiconductor technology have facilitated the development ofsmaller and smaller integrated circuits over the past thirty years;presently, industry possesses adequate technology to fabricatecomputers, telephones, scanners and video cameras which can fit within ashirt pocket, and these devices tend to be more affordable than theirlarger predecessors. Much of these size reductions have been facilitatedby design of smaller and smaller silicon chips, typically based onreductions of minimum silicon (electrical trace) geometry alone.

Conventionally, the silicon chips are mounted to a carrier, the use ofwhich facilitates testing of the chip prior to mounting to a printedcircuit board ("PCB"); use of a carrier also enables redistribution ofthe pitch of input and output connections to be more compatible with PCBtechnology, and replacement of defective chips following mounting.Typically, the carrier is larger than the chip itself and together, thechip and carrier form a "package" which is the commonly recognized ICseen in retail stores. An IC can sometimes also take the form of adirect chip attach (DCA), where the a chip alone is directly mounted toa PCB (e.g., so-called "flip chip technology"). Each of thesearrangements have certain advantages, although to date, DCA is notgenerally used for expensive equipment, but rather is used forinexpensive products that can simply be discarded if inoperable (DCA hasnot to date yielded a process suitable for easy chip replacement).Whichever form of IC mounting is used, the ICs are generallyindividually mounted to a PCB, which can mount many chips and have anumber of off-board connections for connecting other PCBs.

As the size of the ICs continues to decrease, however, it isincreasingly difficult to obtain further reductions in product size byrelying solely upon reductions in minimum silicon geometry. To achievefurther product size reductions, therefore, some recent design effortshave been devoted toward space savings achieved by stacking ICsvertically on top of one another, especially in connection with memorytechnology. These design efforts have generally focused on providingever increasing amounts of integrated circuits into a smaller andsmaller space, to thereby enable design of even smaller computers,telephones, scanners, video cameras, etcetera.

The design efforts devoted toward stacking ICs typically employ aspecial carrier which has wire leads which emanate laterally from thepackage for mounting to a peripheral frame. The peripheral frameprovides structural support for the packages, and also carries anelectrical bus for connection to the individual wire leads of eachpackage. The vertically-stacked packages are then laminated or mademoisture resistant, and are eventually mounted as a single unit to thePCB.

For the space savings achieved, however, the recent design efforts haverequired a relatively labor intensive and costly assembly betweenseparate packages, typically using hardwired assembly between separatepackages. In addition, because the chips generate heat during operation,one design consideration is the presence of structure which permits heatto escape from within the stacked packages, for dissipation outside theframe. Such structure generally further adds to the cost and complexityof the assembly.

There exists a definite need for a three-dimensional chip assembly,useable for both memory chips and other integrated circuits, whichprovides for easy and efficient assembly and electrical connection ofvertically-stacked chips. Preferably, such an assembly should be verylow-cost and be compatible with existing interconnect and PCBtechnology. Further still, such an assembly should include an efficientmethod of heat dissipation. The present invention solves these needs andprovides further, related advantages.

SUMMARY

The present invention provides a three-dimensional chip assembly andrelated method that solves the aforementioned needs. In particular, thepresent invention relies upon a substrate that, contrary to conventionalwisdom, is deliberately made larger in lateral dimension than chip size.By using relatively large scale solder bumps in a free area of thesubstrate (laterally adjacent to the chip or package), the solder bumpsprovide electrical connection to another substrate in a manner thatmultiple substrates can be stacked in parallel. By employingconventional PCB technology to provide connections through thesubstrates and to dissipate heat laterally across the substrates, thepresent invention eliminates the need for complicated or labor-intensivemounting procedures, such as for special frames and the like. Thepresent invention provides a low-cost method of makingvertically-stacked multiple chip assemblies, and it facilitates thetrend toward smaller and less expensive consumer products.

One form of the present invention provides an assembly having at leasttwo ICs that are stacked above one another. The bottom IC (which may bea chip with or without a supporting carrier) is smaller in surface areathan a bottom substrate, such that a "free area" of the bottom substrateis defined which is not masked following attachment of the IC. In this"free area," solder bumps are deposited to have sufficient height so asto mount another, top substrate above the IC. Multiple ICs can be allconfigured and supported in this manner, such that they may be stackedon top of one another.

More particularly, solder balls are used to mount substrates directly inparallel, sandwiching chips and any intervening carriers between thesubstrates. Each substrate has on its bottom side a thermally conductivelayer, which directly contacts the underlying chip, to allow forperipheral heat dissipation during chip operation. By permitting somedeformation of the solder balls during assembly, adjacent IC layers maybe compressed together to bring each chip into contact with the heatdissipating layer of the adjacent IC layer.

The invention may be better understood by referring to the followingdetailed description, which should be read in conjunction with theaccompanying drawings. The detailed description of a particularpreferred embodiment, set out below to enable one to build and use oneparticular implementation of the invention, is not intended to limit theenumerated claims, but to serve as a particular example thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a multiple chip assembly having three IClayers; the assembly is seen as flipped and mounted to a printed circuitboard ("PCB").

FIG. 2 is a perspective view of a single IC layer of the assembly ofFIG. 1; the layer includes an IC, consisting of a chip and carrier,which is mounted atop a supporting substrate; solder balls are seen aspositioned in a free area of the substrate not masked by the IC.

FIG. 3 is a side view of a single layer of FIG. 2, which shows optionalthrough-hole connectors for conducting heat vertically rough theassembly; as seen in FIG. 3, the IC, consisting of a chip and carrier,may also be mounted using solder balls of relatively small pitch.

FIG. 4 is a perspective view of a bottom side of a substrate of FIG. 3,namely, which shows a thermal transport layer for dissipating heatlaterally away from a chip that will contact the bottom side; solderballs are illustrated upon to bonding pads on the bottom side, with somesolder balls (connected to the thermal transport layer) used forvertical heat transfer, and other solder balls (not connected to thethermal transport layer) used for vertical propagation of a logic busthroughout the assembly.

FIG. 5 is a top view of a portion of a substrate, which illustratespositioning of bonding pads with respect to through-hole connections.

FIG. 6 is a side view of a portion of the substrate of FIG. 5, takenalong lines 6--6 of FIG. 5, and illustrates a routing of electricalconnections within multiple layers of the substrate or PCB.

FIG. 7 is a perspective view of two layers of an assembly of FIG. 1,namely, a single layer seen in FIG. 2 with another, identical layerwhich has been mounted vertically above the single layer; an IC seen inFIG. 2 is now illustrated in phantom, as it lies between the two layersof FIG. 7.

FIG. 8 is a side view of a multiple chip assembly of FIG. 7, andindicates preferred use of solder balls to perform both interconnectionof an IC to a corresponding substrate, as well as interconnectionbetween adjacent substrates; the solder balls which connect substratesare seen as preferably mounting substrates flush against adjacent chipsfor peripheral thermal dissipation.

FIG. 9 is a side view of a multiple chip assembly of FIG. 1, includingthree layers which have been connected together, inverted, and mountedupon a printed circuit board ("PCB").

DETAILED DESCRIPTION

The invention summarized above and defined by the enumerated claims maybe better understood by referring to the following detailed description,which should be read in conjunction with the accompanying drawings. Thisdetailed description of a particular preferred embodiment, set out belowto enable one to build and use one particular implementation of theinvention, is not intended to limit the enumerated claims, but to serveas a particular example thereof. The particular example set out below isthe preferred specific implementation of a multiple chip assembly,namely, one which uses solder balls to mount substrates above eachother, notwithstanding the presence of chips or ICs there between. Theinvention, however, may also be applied to other types of systems aswell.

I. Introduction To The Principal Parts.

In accordance with the present invention and as seen in FIG. 1, thepreferred embodiment is a three-dimensional assembly 11 that featuresmultiple integrated circuit ("IC") layers 13 which arevertically-stacked above one another. Each layer includes both an IC(seen in phantom in FIG. 1) and a supporting substrate 15, oriented suchthat the IC and supporting substrate face downward toward a printedcircuit board ("PCB") 17. Each IC performs logic or storage functions inresponse to electrical signals, and these functions may be the same ordifferent across multiple IC layers 13 of the assembly; that is to say,while the preferred embodiment is a memory module, with each layerhaving similar dynamic random access memory ("DRAM") ICs, differenttypes of ICs can also be used (e.g., one layer having a microprocessor,a second layer having memory). FIG. 1 shows three IC layers which areall structurally and electrically connected together by a number ofsolder bumps 19, which also connect the assembly to the PCB 17. AlthoughFIG. 1 shows only three IC layers, it should be understood that anynumber of IC layers can be stacked over the PCB. Also, the downwardmounting of the IC layers 13 is one possible orientation, and the layersmay also be oriented to face upward. The mounting of the assembly 11with individual IC layer substrates 15 parallel to the PCB 19 is alsonot the only configuration contemplated by the present invention, whichcould feature ICs stacked along any direction, e.g., with substratesmounted to the PCB along one of their lateral edges.

Although not seen in FIG. 1, the PCB 17 mounts other circuits which arenot part of the multiple chip assembly, at different locations along theboard's lateral dimensions, "L" (for length) and "W" (for width). Inaccordance with the present invention, however, and as seen in FIG. 1,the ICs of the three-dimensional assembly 11 are stacked vertically,i.e., such that they are adjacent and occupy all three dimensions "H,""L" and "W," to achieve space savings. In addition, each IC includes amechanism for permitting lateral heat dissipation in between layers.

A single IC layer 13 is seen in FIG. 2 with an IC 21 facing upward; theIC is seen to include both a silicon chip 23 and a carrier 25 whichmounts the chip, in a preferred one-to-one (chip-to-substrate)configuration. Notably, one-to-one correspondence between the chips andsubstrates is not required, and alternative configurations can featuremultiple ICs on each substrate. ICs can also be configured in a flipchip configuration if desired, e.g., such that a chip is directlyattached to a supporting substrate without a carrier. The mounting ofthe IC 21 upon each substrate 15 defines a free area 27 of the substratewhich is not masked by any IC; in other words, contrary to tendenciestoward chip scale packages prevalent in second level interconnection,the preferred embodiment deliberately relies upon mismatched areabetween a chip or package and supporting substrate for the purpose ofproviding electrical connection and thermal dissipation between adjacentIC layers.

To this end, as seen in FIG. 3, each substrate 15 is substantially flat,and solder bumps 19 are deposited upon prearranged bonding pads 31within a free area 27 to provide both electrical interconnection betweenlayers as well as vertical thermal transport for heat dissipation.Basically stated, there are two types of solder bumps between layers,including bumps which vertically route a logic bus through the assembly,and bumps which vertically connect lateral thermal layers of all IClayers. The arrangement of the various bonding pads within the free areacan be generally defined by lateral positioning of through-holeconnections 33 which correspond to the bonding pads. In mostapplications, for example, memory technology applications, thedimensions of all substrates and positioning of through-hole connectionsare preferably made constant across all IC layers. In this manner, theassembly provides for roughly linear vertical propagation of a logic busalong the height dimension "H." Each substrate also includes vias (notseen in FIG. 3), either on a top planar surface 35 of the substrate orwithin the substrate's thickness, which connect the IC 21 to otherbonding pads 37 for directly mounting the IC to the particularsubstrate.

Lateral heat dissipation occurs through two layers 38 and 40 indicatedin FIG. 3. A first layer, 38, is formed from a heat conductor, such asan adhesive conductive tape which is layered on top of the IC 21 (andmore particularly the chip 23) after connection of the IC to thesubstrate (i.e., after second level interconnection). A second layer 40is found on the underside of each substrate, and is deposited for thepurpose of continued lateral heat dissipation to lateral edges of eachsubstrate and for coupling to solder bumps used for vertical heatdissipation. The second layer is formed of Organic-Coated Copper ("OCC")and preferably spans a substantial area of the substrate, in a mannerthat will be explained below. When IC layers 13 are stacked upon oneanother, it is intended that the second layer 40 of one IC layer willdirectly abut the first layer of a second IC layer, and so on, such thatthey together form a thermal transport mechanism for conducting heatfrom the chip 23 laterally away from the chip, in a directionperpendicular to the height dimension "H". The second layer 40 of eachIC layer 13 is optionally coupled to certain (but not all) solder bumps19, which provide for vertical heat transport through the assembly.

The multiple chip assembly 11 is fabricated through a series of tasksthat preferably first constructs each IC layer, then stacks the layersand compresses them together to form the assembly, and then mounts theassembly upon the PCB; the last two steps may also be combined. FIGS.2-6 show a single layer of the assembly, while FIGS. 7-8 show a stackingof two layers. FIG. 9 illustrates a stacking of three IC layers, inwhich the IC layers have been inverted to face downward toward a PCB.

II. IC to Substrate Attachment and Substrate Configuration.

Attachment of the IC to the substrate is performed using conventionalmethods of attachment of a chip to a PCB. Consequently, use of flip chipattachment or a package attachment might be suitable, depending upon theparticular application desired. Since the preferred assembly featuresuse of identical DRAM chips within each IC layer 13, it is presentlypreferred to use a package attachment process for such chips.

As is well-recognized by persons skilled in electronic assembly, thechoice of attachment process will many times depend upon the type ofpackage utilized. For example, one package gaining interest in theindustry utilizes a conductive tape which is first attached to a chip,and then attached to a substrate beneath the chip; the tape itself formsthe carrier in this type of arrangement and has through-tape vias thatpermit one side of the tape to be electrically connected to the chip anda second side of the tape to be electrically connected to the substrate.Another process, illustrated in FIGS. 3 and 6-8, utilizes relativelysmall size lead solder bumps 39 which electrically connect the IC 21 toits corresponding substrate 15. It is well-recognized in the art thatthe type of process utilized is a matter of design choice; irrespectiveof the particular process used, the term "first level interconnection"generally refers to electrical coupling of a chip 23 to a carrier 25(e.g., in forming a package, seen in FIG. 2), and second levelinterconnection refers to connection of a carrier (and thus the package)to a substrate 15. Preferably, the first and second levelinterconnection methodologies use a relatively high temperature solderjoint (i.e., using a temperature that is somewhat greater than themelting point of the solder bumps used between different IC layers).

In the preferred embodiment where DRAM chips are used, a solder bumpformation process is used to attach a package to each substrate 15, thatis, to perform second level interconnection. There are many types ofsolder bump formation processes; typically, the processes rely upon acomplex series of deposition procedures which apply solder overnumerous, discrete areas, and then, perform simultaneous attachment ofall solder bumps to achieve electrical connection. The preferredinterconnection process for connecting ICs to each substrate utilizespre-fabricated solder balls, bonding pads and through-layer vias.Preferably also, a solder is used consisting of tin and lead and havinga melting temperature on the order of three-hundred degrees Celsius.These materials are chosen to impart a relatively higher meltingtemperature than bonding pads used for interconnection betweensubstrates (described below) such that, during connection betweenmultiple IC layers, the electrical and structural connection betweenchip and substrate will not be affected. It is also generally desirableto have an under fill between the chip and the package substrate,thereby encapsulating solder balls in order to reduce damage fromthermal cycling in normal operation of the chips, although an under fillis not explicitly illustrated in the accompanying figures. As can beseen from the figures, each substrate 15 is a miniature multilayercircuit board having electrical connections within each one of severallayers.

FIG. 4 presents a perspective view of the bottom of one substrate, whileFIG. 5 presents a cross-section of a part of one substrate.

As indicated by FIG. 4, a substrate 15 has on its bottom surface bondingpads that receive solder balls 41 or 43 for second level interconnection(that is, for connection vertically to other ICs). Notably, two types ofconnections are indicated by FIG. 4, including solder ball connections41 used for vertical thermal transport (between layers and to the PCB)and solder balls connections 43 for vertical logic bus propagation. Tothis effect, the second thermal transport layer 40 on the bottom of eachsubstrate is patterned of organic-coated copper ("OCC") during substratemanufacture to preferably connect to every third or fourth solder ball,as indicated in FIG. 4. This thermal transport layer, as has previouslybeen described, is placed in direct contact with a chip of an underlyingIC layer (or more accurately, layers 38 and 40 on the top of the IC andthe bottom of a substrate are combined to form a thermal transport layerthat directly contacts an IC or package), and is used to dissipate heatfrom the chip peripherally, toward the lateral edges of the assembly. Itshould be understood that FIG. 4 illustrates a relatively small numberof solder ball connections, and a hypothetical thermal transportpattern, and that one skilled in the art should be able to readilyselect an appropriate pattern depending upon the desired application.

Arrangement of bonding pads upon the substrate is further illustrated inFIG. 5, which shows a cut-away top view of part of a substrate. As seenin FIG. 5, a first group of bonding pads 31 (for solder ball connectionsbetween substrates) are positioned adjacent to hole connections 33.Surface traces 32 couple corresponding bonding pads 31 and through holeconnections 33, so as to prevent wicking of solder by the through-holeconnection. Also seen in FIG. 5 are a second group of bonding pads 37used to mount one or more ICs to the substrate 15. In-substrate vias(not seen in FIG. 5), couple this second group of bonding pads 37 tocorresponding through hole connections. Importantly, some of the firstgroup of bonding pads 31 are used for vertical thermal transport, andtherefore, have no corresponding IC connection (e.g., bonding pad 37).

This relationship is further illustrated by FIG. 6, which is a crosssection of part of the substrate seen in FIG. 5, taken along lines 6--6of FIG. 5. More particularly, as seen in FIG. 6, bonding pads 31 forinter-substrate connection are located on top and bottom sides of thesubstrate 15, slightly offset from a corresponding through-holeconnection 33. A surface trace 32 on each side of the substrate connectsthe two together. As seen at the left side of FIG. 6, an IC bonding pad37 is also coupled to the through-hole connection 33 by an inner trace45 which is in a middle layer of the substrate. All of the couplingmaterials are formed of copper, with a non-oxidizing material such as anorganic coating capping layers which are exposed to air.

III. Interconnection Between Adjacent Layers And To PCB.

Interconnection between layers will be explained with reference to FIGS.7-9. While FIGS. 7 and 8 in particular show only two IC layers, itshould be understood that the preferred attachment process between IClayers and between, a between an IC layer or finished assembly and thePCB, are identical; consequently, attachment of any two IC layers could,in the context of the present invention, be taken to either be IC layers(designated by reference numeral 13 in FIGS. 1-3), or a single substrate15 of a "bottom" IC layer and the PCB 17. However, it will be assumedfor purposes of the discussion below that two substrates that are to beconnected represent two IC layer substrates already having chips mountedupon them.

FIG. 7 shows a first substrate 51 and a second substrate 57 which areconnected together by solder balls 19. In accordance with the principlesdescribed above for forming each IC layer, solder balls are mounted onsubstrates 51 and 57 laterally adjacent to an IC 63 or 65. In formingconnection between layers, the solder balls 19 are preferablypre-deposited on the top side 59 of each substrate. The substrates,solder balls and associated pads are aligned, and then are heated to atemperature sufficient to melt the solder balls and bring the substrates(and associated heat conducting layers 40) into direct contact withunderlying ICs.

This relationship is illustrated by FIG. 8, which shows that the bottomside 61 of the first substrate has been brought into direct contact witha top side 62 of the IC 63 of the underlying layer. While the solderballs are originally spherical (as indicated, for example, by FIG. 3),heating of the assembly and tendency of the solder balls 19 to spread toadhere to associated bonding pads 31 causes the solder balls to becomemolten and deform, to draw the substrates together to sandwich ICsbetween them. The solder balls are heated to somewhat over their meltingtemperature, and it is expected that with proper solder ball 19 size andbonding pad 31 size and geometry, surface tension of the solder shouldprovide sufficient force to bring substrates into contact with the ICsof adjacent layers. A clamping mechanism could potentially be usedduring the heating procedure to ensure elimination of any space betweenan IC and the substrate from an adjacent layer, although it is expectedthat such should not be necessary and would increase production cost. Itshould also be noted that the solder balls are designed to have massthat falls within a narrow tolerance, i.e., such that there is enoughsolder to wet the bonding pads, but not so much solder as to createelectrical shorts with other, adjacent bonding pads. Preferably,eutectic tin-bismuth solder balls 19 are used for the solder connection,and the bonding pads preferably are formed of OCC, so that when thesolder balls 19 melt, they provide a suitable bond to these pads. Moreparticularly, the solder balls are formed of a 58% tin, 42% bismuthalloy, which has a melting temperature of approximately 138 degreesCelsius. For improving solder joint strength and reliability, this 58/42mixture can be supplemented by an approximately zero-to-two percent byweight quantity of silver.

To mount IC layers 13 together, as seen in FIGS. 2, 7 and 8, a firstsubstrate 51 is aligned with a second substrate 57 to place the solderballs 19 directly in contact with the bonding pads and a bottom side 61of the second substrate 57. The solder balls 19, being formed of arelatively low-temperature metal, are softened without disturbing theintegrity of the connections which mount an IC to either substrate 51 or57. Preferably, all IC layers of the assembly seen in FIG. 1 are coupledtogether simultaneously and, so, solder balls would have already beenmounted to the top of each (e.g., the top side 53 of each) substrate,with all substrates in the assembly being aligned and mounted to eachother at the same time. At the same time, the layers are compressedtogether while the solder balls are softened to bring a first thermaltransport layer 38 of each IC into direct contact with a second thermaltransport layer 40 on the bottom of each IC, as illustrated in FIG. 8.As a result, heat is dissipated laterally, along the dimensions "W" and"L" as identified in the different perspectives presented in FIGS. 1-9.

Attachment and mounting together of the multiple IC layers upon a PCB isbest seen with reference to FIG. 9. In particular, the assembly is seento consist of three IC layers 66 which have been stacked on top of eachother using solder balls 67. A set of bonding pads 68, formed of OCC,are positioned on the PCB 70 so as to align with bonding pads andassociated solder balls of a top layer 71 of the assembly, which hasbeen inverted with respect to the PCB. Via a heating process, the solderballs are made to melt, with the assembly properly oriented on top ofthe PCB, such that strong and reliable connections are formed betweenthe assembly and the PCB. Notably, since the substrate 73 of a bottom IClayer is made of substantially the same material as the PCB 70, therewill be insignificant thermal mismatch between the assembly 11 and thePCB, and an under fill need not be added to support mounting of theassembly.

The preferred multiple chip assembly 11 just described is notnecessarily intended for application to all potential three-dimensionalcombinations of ICs. Notably, while the thicknesses of the heattransport layers (38 and 40, seen in FIG. 3) can be varied in accordancewith different desired applications, there may be some applicationswhich require additional and substantial cooling arrangements. Forexample, it is well understood in the art that some chips generate verylarge amounts of heat, sometimes requiring dedicated fans and othercooling arrangements, and use of lateral heat transport through heattransport layers, as described herein, may provide insufficient for somechips in some applications.

Various modifications of what has been described will readily occur tothose of ordinary skill in the art without departing from the principlesof the present invention. For example, one could stack ICs in adifferent configuration than has been illustrated in connection with theaccompanying figures. Also, one could use the IC layer arrangement justdescribed to mount different types of chips either on the same IC layeror across multiple layers, e.g., a microprocessor chip and a memory chipcould both be mounted within the assembly. The particular use ofthrough-hole connections for running a bus vertically through allsubstrates (to service all chips in the assembly) or vias withinsubstrates are not the only possible implementations for electricallyconnecting together the multiple layers according to the presentinvention. Also, one could mount IC layers together without providing aseparation between ICs and the substrates of adjacent layers.

Having thus described several exemplary embodiments of the invention, itwill be apparent that various alterations, modifications, andimprovements will readily occur to those skilled in the art. Suchalterations, modifications, and improvements, though not expresslydescribed above, are nonetheless intended and implied to be within thespirit and scope of the invention. Accordingly, the foregoing discussionis intended to be illustrative only; the invention is limited anddefined only by the following claims and equivalents thereto.

We claim:
 1. A multiple chip assembly, comprising:a first integratedcircuit mounted upon a first substrate; a second integrated circuitmounted upon a second substrate, the second integrated circuit having aheight associated with it, the second integrated circuit also beingoverlapped by the second substrate in at least one of width and lengthdimensions, such that the second substrate presents a free area notmasked by the second integrated circuit; and solder bumps which provideelectrical interconnection between the first and second substrates, thesolder bumps being at least as tall as the height of the secondintegrated circuit to thereby electrically mount the first substrate ina stacked relation above the second integrated circuit; a thermaltransport layer in between and in contact with each of the secondintegrated circuit and the first substrate; whereinthe second substrateincludes (on a side of the second substrate which mounts the secondintegrated circuit), in the free area, electrical terminations forelectrical interconnection to the first substrate, the first substrateincludes corresponding electrical terminations for electricalinterconnection to the second substrate, and the solder bumps connectthe electrical terminations of the second substrate with thecorresponding electrical terminations of the first substrate.
 2. Amultiple chip assembly according to claim 1, wherein the secondintegrated circuit includes both a chip and a carrier, the chip mountedto the carrier by a first level interconnection, and the carrier mountedto the second substrate by a second level interconnection.
 3. A multiplechip assembly according to claim 2, wherein both the second levelinterconnection and the electrical interconnection between the first andsecond substrates are made using solder bumps.
 4. A multiple chipassembly according to claim 1, wherein electrical terminations forelectrical interconnection to the second substrate are mounted on a sideof the first substrate opposite the first integrated circuit.
 5. Amultiple chip assembly according to claim 1, wherein each substratemounts a single integrated circuit only, such that there is a one-to-onecorrespondence between each chip and each substrate in said assembly. 6.A multiple chip assembly according to claim 1, wherein the thermaltransport layer includes both a first transport layer mounted on a topof the second chip, and a second thermal transport layer mounted on abottom of the first substrate.
 7. A multiple chip assembly according toclaim 1, further comprising:a second level interconnection whichconnects the second chip to the second substrate; and a substrateinterconnection which connects the first substrate to the secondsubstrate; wherein a melting temperature associated with the secondlevel interconnection is substantially less than a melting temperatureassociated with the first level interconnection.
 8. A multiple chipassembly according to claim 7 wherein the second level interconnectionhas an associated melting temperature that is greater than two hundredand fifty degrees Celsius and the substrate interconnection has anassociated melting temperature that is less than one hundred and fiftydegrees Celsius.
 9. An improvement in a stacked multiple chip assembly,the multiple chip assembly including at least first and secondintegrated circuit layers in stacked relation, each layer including atleast one chip and a substrate, all substrates being electricallyconnected together, comprising:for the second layer, using a chip andsubstrate combination with non-matched area, such that the substrateoverlaps the chip in at least one lateral dimension, to define a freearea in the substrate which is not masked by the chip; electricalterminations in the free area arranged to provide electricalinterconnection between the first and second layers; solder bumpsproviding the electrical interconnection, the solder bumps having anassociated height dimension sufficient to directly mount the substrateof the first layer upon the substrate of the second layer, also aboveeach chip mounted upon the second layer; and a thermal transport layerdirectly in contact with a chip of the second layer and a bottom of thesubstrate of the first layer.
 10. An improvement according to claim 9,further comprising:a carrier which intervenes between at least one chipand a corresponding substrate that mounts the chip; a first levelinterconnection which electrically connects and mounts the at least onechip to the corresponding carrier; and a second level interconnectionwhich electrically connects and mounts the corresponding carrier to thesecond substrate.
 11. An improvement according to claim 10, furthercomprising providing the electrical interconnection between layersby:forming the second level interconnection to have solder bumps whichmelt at a lower temperature than melting point of the first levelinterconnection; and placing the solder bumps in contact with electricalterminations and heating the solder balls and electrical terminations toa temperature which melts the solder bumps but does not fully melt thefirst level interconnection.
 12. An improvement according to claim 11,further comprising:forming the solder bumps to initially have a heightgreater than any chip between the first and second layers afterelectrical connection, to thereby initially place the first substrate inspaced relation above any intervening chips; and subsequently heatingthe solder bumps to a temperature which at least partially melts themand permits compression of two layers toward each other to eliminate thespaced relation while the solder bumps are heated.
 13. A method ofstacking multiple chips, using first and second integrated circuits andassociated first and second substrates, the second substrate selected tobe larger in at least one lateral dimension than the second integratedcircuit, such that the relative dimensions of the second integratedcircuit and second substrate are not matched, the first substrate havinga bottom side with a thermal transport layer that substantially spansthe bottom side, comprising:forming a first set of substrateinterconnection pads on top of the second substrate within a free areanot masked by the second integrated circuit, to provide for electricalinterconnection between the first substrate and the second substrate;forming a second set of substrate interconnection pads on bottom of thefirst substrate to provide electrical interconnection between the firstsubstrate and the second substrate, the second set of substrateinterconnection pads aligned for electrical interconnection with thefirst set of substrate interconnection pads when the substrates areplaced in proximity to one another; depositing solder bumps on at leastone of the first set and second set of substrate interconnection pads;mounting the first integrated circuit on top of the first substrate andmounting the second integrated circuit on top of the second substrate;mounting the first substrate on top of the second substrate and abovethe second integrated circuit, with the solder bumps providingelectrical interconnection between substrates, with the secondintegrated circuit there between; and heating the first and secondsubstrates and solder bumps, and removing space between the firstsubstrate and the second integrated circuit, to bring the thermaltransport layer into contact with the second integrated circuit.
 14. Amethod according to claim 13, further comprising simultaneously stackingat least three chips and associated substrates, using solder bumps toelectrically connect substrates to one another, by:first mounting chipson each substrate; and heating together the chips and the substrates toa temperature sufficient to melt the solder bumps and bring the chipsand substrates together, such that at least portion of an underside ofone substrate comes into direct contact with at least one chip ofanother substrate.
 15. A method according to claim 13, furthercomprising using heat and solder surface tension to draw the firstsubstrate and the second integrated circuit together, to remove spacebetween the first substrate and the second integrated circuit.